Análise de Desempenho de um Roteador utilizando Diferentes Arquiteturas de Decremento em uma Rede-em-Chip
DOI:
https://doi.org/10.5540/tema.2008.09.03.0427Abstract
Uma rede-em-chip está sendo desenvolvida para permitir a implementação de uma Rede de Petri em hardware. Para determinar a melhor arquitetura do decrementador a ser incorporada ao roteador dessa rede foi desenvolvida uma abordagem baseada em equações matemáticas que computam as quantidades de portas lógicas e de níveis de lógica dos decrementadores e do roteador. Uma fórmula de desempenho foi estabelecida para realizar uma análise comparativa da arquitetura do roteador com cada um dos decrementadores.References
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